ISSN(online):2394-3785

ISSN(Print):2394-3777

INTERNATIONAL JOURNAL OF ADVANCED RESEARCH TRENDS IN ENGINEERING AND TECHNOLOGY

A monthly peer reviewed Engineering, Science & Technology Journal

Volume 4,Special Issue 23,December 2017

Title Authors Download QR CODE
DESIGN OF T LATCHES BASED ON REVERSIBLE QUANTUM DOT CELLULAR AUTOMATA Ms.Amutha.V,Ms.Geeta.R,Dr.Ramasamy.K Full paper

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10.20247/IJARTET.2017.0412001
Sierpinski Fractal Antenna for SWB Application Ms.Arumugapriya.E,Mr.Sathis kumar.N.R,Dr.Ramasamy.K Full paper

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10.20247/IJARTET.2017.04S2312002
Analysis of Low Power CMOS Dual Edge Triggered Flip Flops Using Multiple C Elements J.ROSIANJALIN, G.SATHYA, Dr.K.RAMASAMY Full paper

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10.20247/IJARTET.2017.04S2312003
CLASSIFICATION OF SEIZURE AND NON SEIZURE EEG SIGNAL USING NEURAL NETWORK CLASSIFIER K.Priyadharshini, V.Krishna meera, Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S2312004
Fault Tolerance Technique Using MSR Logic For Combinational Circuits Ms.Kodieswari.P,Ms.Geeta.R,Dr.Ramasamy.K Full paper

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10.20247/IJARTET.2017.04S2312005
Using Balanced Data Distribution Scheme for Energy hole Avoidance in UWSN MsKowsalya.M, Mrs.Maheshwari.J, Dr.Ramasamy.K Full paper

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10.20247/IJARTET.2017.04S2312006
Implementation of SHA 5 Algorithm using Adaptive Channel aware detection of attacks in WSN Ms Murugalakshmi.M,Mrs.A.R.Devi,Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S2312007
DESIGN OF ASYNCHRONOUS LOGIC QDI CELL TEMPLATE USING CURRENT CONTROLLED LATCH A.Nagalakshmi, M.Durgadevi, Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S2312008
Design, Analysis and Implementation of PNAND Cell Using Sense Amplifier Energy Recovery Flip Flop R.Rajamuthu petchi, B.Dhanam, Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S2312009
EFFICIENT POWER REDUCTION OF STATIC RANDOM ACCESS MEMORY S.Banupriya, B.Dhanam, Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S23120010
REDUCTION OF COUPLING SIGNALS USING LATCH TYPE SENSE AMPLIFIER IN SRAM T.Vaishubiah, M.Durgadevi, Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S23120011
Design and Analysis of Time to Digital Converter Based on Vernier Delay Line Ms. Veeralakshmi @ Veena.K, Ms. Durga Devi.M, Dr. Ramasamy.K Full paper

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10.20247/IJARTET.2017.04S23120012
DESIGN,ANALYSIS AND IMPLEMENTATION OF VARIOUS FULL ADDER USING GDI AND MGDI TECHNIQUE Ms. Vishalatchi.S, Ms. Dhanam.B, Dr. Ramasamy.K Full paper

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10.20247/IJARTET.2017.04S23120013
Efficient approach to design a reversible fault tolerant division unit using Quantum dot cellular automata A.Abiraha,V.Krishna meera,Dr.K.Ramasamy Full paper

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10.20247/IJARTET.2017.04S23120014
Integration Technique for Health Care Allied Equipment using Transistor Dense Flip Flop Dr.J.Jasper Gnana Chandaran Full paper

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10.20247/IJARTET.2017.04S23120015